1. Field of the Invention
The present invention relates to a semiconductor device and an information processing system including the semiconductor device, and more particularly relates to a semiconductor device that uses a multi-phase clock signal with different phases and an information processing system including the semiconductor device.
2. Description of Related Art
Many semiconductor devices operate synchronously with a clock signal and some of the semiconductor devices use a multi-phase clock signal with different phases. Because the multi-phase clock signal has a phase interval shorter than a cycle of a base clock signal, how the multi-phase clock signal is generated becomes a problem.
As an example of a circuit that generates a multi-phase clock signal with a shorter phase interval, Japanese Patent Application Laid-open No. 2010-16545 discloses a circuit in which plural kinds of delay elements having different delay amounts are cascade-connected. With the multi-phase-clock generating circuit described in Japanese Patent Application Laid-open No. 2010-16545, the phase interval of the multi-phase clock signal can be shorter than a minimum delay time corresponding to one stage of delay elements.
However, the multi-phase-clock generating circuit described in Japanese Patent Application Laid-open No. 2010-16545 needs a number of delay elements to generate one of signals constituting the multi-phase clock signal. Accordingly, it is necessary to use so many delay elements in the whole circuit, which greatly increases the circuit scale.
The amount of data to be handled by a semiconductor device increases year by year and a processing speed thereof tends to be accelerated. Therefore, it is required that an information processing system that processes such a large amount of data at a high speed and reduces a required circuit scale, and a semiconductor device included in the system.